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august 2013 docid023948 rev 1 1/16 AN4208 application note 300 m flip chip package description and recommendations for use introduction this document provides package and usage recommendation information for 300 m pitch flip chips assembled on board pitch 400 m. for information on 400 m flip chips, see application note an2348. the competitive market of portable equipmen t, notably the mobile phone market, is driven by a challenging development of highly integrated products. to allow manufacturers of portable equipment to reduce the dimension of their products, stmicroelectronics has developed packages with reduced size, thickness and weight in the form of the flip chip. the electrical performance of such components in flip chips is improved thanks to shorter connections than the ones in standard plasti c packages (such as tssop, ssop or bga). figure 1. typical flip-chip package the flip-chip package family has been designed to fulfill the same qua lity levels and the same reliability performances as standard semic onductor plastic pack ages. this means these new flip-chip packages should be considered as new surface mount devices which will be assembled on a printed ci rcuit board (pcb) wi thout any special or additional process steps required. in particular this package does not require any extra underfill to increase reliability performances or to pr otect the device. this package is compatible with existing pick and place equipment for board mounting. only lead-free, rohs compliant flip chips are available in mass production. this application note addresses the following topics: ? product description ? mechanical description ? packing specifications and labeling description ? recommended storage and shipping instructions ? soldering assembly recommendations ? user responsibility and returns ? changes ? delivery quantity ? quality tm: ipad is a trademark of stmicroelectronics b 1 2 a www.st.com
product description AN4208 2/16 docid023948 rev 1 1 product description flip chips are manufactured with a wafer level process that stmicroelectronics has developed by attaching solder bumps on i/o pa ds of the active wafer side, thus allowing bumped dice to be produced. the i/o contact layout can be either matrix shape or set in periphery. no redistribution layer is used. this allows parasitic induct ances coming from the redistribution metal tracks to be minimized. lead-free bump composition is 96.5% sn, 3% ag, 0.5% cu. this is fully compatible with standard lead-free reflow processes. the bump dimension (175 m bump diameter) allows the pick and place process to be compatible with existing equipment (in particular with equipment used for ball grid ar ray - bga packages) and makes it also compatible with the pcb design rules used for standard ics. optional coating on the flat side of the package is available. these components are delivered in tape and reel packing with the bumps turned down (placed on the bottom of the carrier tape cavity). the other face of the component is flat and allows picking as in the standard smd packages. devices are 100% electrically tested before packing . the product references are marked on the flat side of the device. 2 mechanical description mechanical dimensions of flip chips ar e provided through a product example in figure 2 . bumps are lead-free. bump composition is 98.25% sn, 1.2% ag, 0.5% cu, 0.05% ni alloy with a near eutectic melting point of 218 to 227 c. die size and bump count are adapted to the connection requirements. figure 2. mechanical dimensions of a 2 x 2 bump matrix array . note: the package height of 0.605 mm (0.650 mm for optionally coated packages) is valid for a die thickness of 0.48 mm. 172 m 172 m 645 m 30 m 645 m 30 m 300 m 30 m 175 m 20 m 120m 300 m 30 605 m 55
docid023948 rev 1 3/16 AN4208 packing specifications and labeling description 16 the flip chip tolerance on bump diameter and bump height are very tight. this constant bump shape insures a good coplanarity between bumps. optical measurements performed through vertical focuses show a bump plus die coplanarity below 50 m. the product marking for the flat side is shown on figure 3 (product example). the flip chip has a pin marker - a1 (see figure 1 ) on both the flat side and the bump side so that the orientation of the component can be easily determined before and after assembly. the dots marked on the flat side and on the bump side have been designed so that they can be detected by standa rd vision systems. marking dimensions are linked to the die size. figure 3. flip chip marking example for 2 x 2 bump matrix array. 3 packing specifications and labeling description flip chips are delivered in tape and reel to be fully compatible with standard high volume smd components. the features of tape and reel materials are in accordance with eia-481-d, iec 60286-3 and eia 763 (783) standards. all features not specified in this section are in accordance with eia-481-d, iec 60286-3 and eia 763 (783) standards. 3.1 carrier tape flip chips are placed in the carrier tape with their bump side facing the bottom of the cavity so that the components can be picked-up by thei r flat side. no flipping of the package is necessary for mounting on pcb. the products are positioned in the carrier tape with pin a1 on the sprocket hole side. carrier tape mechanic al dimensions are shown in the example in figure 4 . standard tape width is 8 mm for die sizes smaller than 3 mm (dimension b0). note: 12 mm carrier tape width may be used for a larger die size to be in line with eia standards. x dot, xx = marking x
packing specifications and labeling description AN4208 4/16 docid023948 rev 1 figure 4. tape dimensions for flip chips less than 0.8 x 0.8 mm (605 m thickness). * a1 bump location varying with product layout user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 0.3 2.0 0.1 1.75 0.1 3.5 - 0.05 ? 1.55 0.05 0.69 0.05 0.20 0.05 0.73 0.05 0.73 0.05 dot identifying pin a1 location x x x x x x x x x x x x x x
docid023948 rev 1 5/16 AN4208 packing specifications and labeling description 16 the cavities in the carrier tape have been designed to avoid any damage to the components. specific hole is present to im prove device stability during sealing and pick up the embossed carrier tape is in a black con ductive material (surfa ce resistivity within 10e5 and 10e11 ohm/sq). use of this material protects the component against damage from electrostatic discharge and ensures the total di scharge of the component prior to placement on the pcb. conductivity is guaranteed to be constant and not affected by shelf life or humidity. the material will not break when bent and does not have any residue to rub off, powder, or flake. 3.2 cover tape the carrier tape is sealed with a transpare nt, anti static (surfa ce resistivity within 10e5 ohm/sq and 10e11 ohm/sq) polyester film cover tape with a heat activated adhesive. the cover tape tensile strength is higher than 10 n. the peeling force of the cover tape is between 0.08 n and 0.5 n in accordance with the testing method eia-481-d and iec 60286-3. co ver tape is peeled back in the direction opposite to the carrier tape travel; the angle between the cover tape and the carrier tape is between 165 and 180 degrees and the test is done at a speed of 120 10% mm/minute. table 1. tape cavity sizing dimension die with both sides smaller than or equal to 1.5 mm die with one side larger than 1.5 mm a0 and b0 die side size + 70 m cavity dimensions established to ensure that component rotation cannot exceed 10 max.
packing specifications and labeling description AN4208 6/16 docid023948 rev 1 3.3 reels the sealed carrier tape with the flip chip is reeled on seven-inch reels (see figure 5 for reel mechanical dimensions). these reels are comp liant with eia-481-c standard. in particular, they are made of an anti static polystyrene material. color of the reel may vary depending on supplier. dice quantity per reel is 5000 or 10000 or 15 000 (with typical package thickness equal to 605 m). in compliance with the iec 60286-3, ea ch reel contains a maximum of 0.1% empty cavities. two successive empty cavities are not allowed. each reel may contain components coming from 2 different wafer lots. each reel has a minimum leader of 400 mm and a minimum trailer of 160 mm (compliant with eia 481-c and iec 60286-3 standards). the leader makes up a portion of carrier tape with empty cavities and sealed by cover tape at the beginning of the reel (external side). the leader is affixed to the last turn of the carrier tape by using adhesive tape. the trailer is at the end of the reel and consists of empty, sealed cavities (see figure 6 ). figure 5. seven-inch reel mechanical dimensions. figure 6. leader and trailer abcde w1 (hub) w2 w3 (external) 180 max all dimensions in mm material: antistatic polystyrene 1.5 min 13 +0.5 8.4 +1.5 8.4 +2.5 20.2 min 60 min 14.4 max -0.2 -0 -0.5 leader no components components no components trailer 100mm min . start 160mm min . 400mm min. leader and trailer end sealed with cover tape user direction of feed to p cover tape
docid023948 rev 1 7/16 AN4208 packing specifications and labeling description 16 3.4 final packing each reel is heat sealed under inert atmosphere in a transparent, recyclable and anti static polyethylene bag (minimum of 4 mils material thickness). reels are then packed in cardboard boxes. the complete description for packing is shown on figure 7 . figure 7. packing flow chart. 3.5 labeling to ensure component traceabilit y, labels are stuck on the re els and the cardboard box. the seven inch reels and the cardboard box are identified by labels including part number, shipped quantity and traceability references ( figure 8 ). the traceability is ensured fo r each production lot and ea ch shipment lot through the labeling. the trace code number printe d on the labels ensures backw ard traceability from the lot received by the customer at each step of the process - in / out dates and quantity at diffusion, assembly, test and final store. likewis e, forward traceability is able to trace a lot history from the wafer fab to the customer?s location. figure 8. example of a reel label dice into the reel reel in a sealed plastic bag within inert atmosphere the reel in its bag is packed in a cardbox for storage & shipment 36 mm 5 assembled in moisture sensitivity level perforation line first type line - commercial product second type line - finished goods bulk quantity 1st trace code line 2nd trace code line marking bulk id number
packing specifications and labeling description AN4208 8/16 docid023948 rev 1 table 2. parameter reel label field field type assembled in mandatory: country of origin pb-free 2 nd . level interconnect as per jedec standard jesd97 msl mandatory for concerned products as defined in mpi moisture sensitivity level as per jedec j-std-020 mandatory for smd bag seal date for msl 2 and above, date of vacuum sealing of dry bag for msl=1, ?not moisture sensit ive? must be printed instead pbt peak package body temperature as jedec j-std-020 mandatory for the smd category pb-free category as pr jedec standard jesd97 mandatory for concerned products as defined in mpi eco level mandatory for ecolevel devices only as defined in mpi type mandatory first line: not required second line: raw line product name total qty mandatory - bulk quantity trace code mandatory- traceability code with wafer fab production area code bulk id mandatory: bulk id number, start with a bar code mandatory: bar code area
docid023948 rev 1 9/16 AN4208 recommended storage, shipping instructions and descriptions 16 4 recommended storage, shipping instructions and descriptions flip-chip reels are packed under inert n 2 atmosphere in a sealed bag. for shipment and handling, reels are packed in a cardboard box. stmicroelectronics thus recommends the fo llowing shipping and storage conditions: ? relative humidity between 15% and 70% ? temperature range from -55 c to +150 c components in a non opened sealed bag can be stored 6 months after shipment. components in tape and reel must be prot ected from exposure to direct sunlight. moisture sensitivity level (msl as per jede c j-std-020c) is not applicable to flip-chip devices since there is no plastic encapsulation and so no risk of moisture absorption and related possible package cracks.
soldering assembly recommendations AN4208 10/16 docid023948 rev 1 5 soldering assembly recommendations 5.1 pcb design recommendation s for multi-bump flip chips for optimum electrical performance and highly reliable solder joints, stmicroelectronics recommends the pcb design guidelines listed in table 3. . note: a too thick gold layer fini shing on the pcb pad is not re commended (low joint reliability). to optimize the natural self ce ntering effect of flip chips on pcb, pcb pad positioning and size have to be properly designed (see figure 9 ). figure 9. multi-bump flip-chip bump footprint micro vias an alternative to routing on the top surface is to route out on buried layers. to achieve this, the pads are connected to the lower layers using micro vias. 5.2 pcb assembly guidelines for flip chip mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 240 m and a typical stencil thickness of 100 m. flip chips are fully compatible with the use of near eutectic 95.8% sn, 3.5% ag, 0.7% cu solder paste with no- clean flux. st's reco mmendations for flip-c hip board mounting are illustrated on the soldering reflow profile shown in figure 10 . table 3. pcb design recommendations. pcb pad design non solder mask defined micro via under bump allowed pcb pad size ? = 220 m recommended / 260 m maximum solder mask opening ? = 300 m minimum pcb pad finishing cu - ni (2-6 m) - au (0.2 m max) or cu osp (organic substrate protection) copper pad diameter: 220m recommended 260 m maximum solder stencil opening: 220m recommended solder mask opening: 300 m minimum
docid023948 rev 1 11/16 AN4208 soldering assembly recommendations 16 figure 10. st ecopack ? recommended soldering reflow profile for flip chip mounting on pcb (definitions) dwell time in the soldering zone (with temperature higher than 220 c) has to be kept as short as possible to prevent component and substrate damages. peak temperature must not exceed 260 c. controlled atmosphere (n 2 or n 2 h 2 ) is recommended during the whole reflow, specially above 150 c. flip chips are able to withsta nd three times the previous recommended reflow profile to be compatible with a double reflow when smds are mounted on both sides of the pcb plus one additional repair. a maximum of three soldering reflows are allowed for these lead-free packages (with repair step included). the use of a no-clean paste is highly reco mmended to avoid any cleaning operation. to prevent any bump cracks, ultrasonic cleaning methods are not recommended. 5.3 underfilling underfilling is not essential for flip chips. t hese devices can do without an underfill if the process temperature does not exceed 175 c a nd if the process time is short (typically 5 minutes). table 4. st ecopack ? recommended soldering reflow profile for flip chip mounting on pcb (value) profile value typical max. temp. gradient in preheat (t = 70 ? 180 c) 0.9 c/s 3 c/s temp. gradient (t = 200 ? 225 c) 2 c/s 3 c/s peak temp. in reflow 240 - 245 c 260 c time above 220 c 60 s 90 s temp. gradient in cooling -2 to - 3 c/s -6 c/s time from 50 to 220 c 160 to 220 s 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
soldering assembly recommendations AN4208 12/16 docid023948 rev 1 5.4 manual rework flip chips are able to tolerate one repair in addition to the two reflows mentioned in section 5.2 . as for other bga type packages the use of laser systems is the most suitable form for flip chip repair. manual hot gas soldering is acceptable but iron soldering is not recommended. for leaded flip chip manual rework the maximum temperature allowed is 260 c (lead-free compatibility) and dwell time must not exceed 30 seconds. for lead-free flip chip manual rework, the maximum temperature allowed is 260 c. the typical soldering profile of figure 10 can be used. 5.4.1 rework procedure remove the device rework process start with the removal of the device. to remove the device, heat must be applied to melt the solder joints so that the component can be lifted from the board. large area bottom side preheaters may be used to raise the temperature of the board. this may help to minimize warping of the board, an d minimize the amount of heat that must be applied on the component. top heating may be applied to the component by using a laser or a convective hot gas nozzle. nozzle size must be se lected to match the component footprint appropriately. after top heating has melted the solder, vacuum is applied through the pick-up nozzle, and the component is lifted from the board. the heat should be carefully directed at the component to be removed to avoid adjacent components solder joints being reflowed. shielding, control of gas flow from the nozzle, and accurate temperature control are the key parameters. removing solder next step is cleaning the solder from the work site. due to space constraints and the need for accurate temperature control, automatic tools are recommended. typically, site cleaners consist of controlled non-contact gas heating and vacuuming tools. the objective is to remove th e residual solder from the site without damaging the pads, solder masks or adjacent components, and to prepare the site for application of new component.
docid023948 rev 1 13/16 AN4208 soldering assembly recommendations 16 new device soldering for placement of the device several solutions are possible: ? use a mini-stencil and solder paste then place the device. this is the preferred solution to ensure homogeneity of assembly conditions if assembly of wlcsp (wafer level chip scale package) is performed with solder paste, even if small footprints and tight dimensions make this operation difficult. ? use no-clean flux on the site and place the device. ? dip the wlcsp in no-clean flux, and to place it on the board. next operation is to reflow the solder joint by applying controlled heat to the component. this can be done in much the same way as described above for component removal, but accurate temperature control is necessary to ensure good soldering of the joint. alternatively this can be done by putt ing the whole board in a furnace. see figure 10 for reflow profile recommendations. equipment systems for these operations are available at various levels of automation. methods and techniques used in more sophisticated autom atic systems can be copied using manual equipment. soldering irons should be avoided fo r these operations. tweezers or any picking tools pressuring the sides or bottom (bump side) of the wlcsp must be avoided since such tools can damage silicon and create chip outs. figure 11 shows an example of semi-automatic eq uipment for component rework. (see the web site of comintec for more information.) figure 11. comintec onyx32 - semi-automatic equipment for component rework
changes AN4208 14/16 docid023948 rev 1 onyx32 key features ? fully automated x,y,z and theta control ? fully automated alignment using digita l feature separation (dfs) technology ? precision force sensor and mass flow controller ? four zone bottom preheater ? flux dipping station ? firewire (ieee 1394) controls ? visual machines software ? machine table including power supply cabinet onyx32 options ? dispensing head for so lder paste, flux, underfill or adhesives ? non-contact temperature sensor ? site solder removal system 6 changes stmicroelectronics reserves the right to implement minor changes of geometry and manufacturing processes without prior notice. such changes will not affect electrical characteristics of the die, the pad layout or the maximum die size. however for confirmed orders, no variation will be made without customer?s approval. 7 quality 7.1 electrical inspection products in flip chip are 100% electrically prob ed according to the critical parameters of the st product specification. the last operation be fore packing is 100% electrical testing. the other parameters are guaranteed by technology , design rules and by continuous monitoring systems. 7.2 visual inspection a visual control is performed on all manufacturing lots according to the mil-std-883 method 2010.
docid023948 rev 1 15/16 AN4208 conclusion 16 8 conclusion lead-free flip-chip packages have been developed by stmicroelectronics for electronic applications where integration and performa nce are the main concerns of designers. stmicroelectronics flip chips offer: ? remarkable board space saving (package size equal to die size and total height less than 605 m) ? enhanced electrical performance (minimized parasitic inductance due to very short electrical paths and absence of redistribution layer) ? high reliability due to integration of a whol e function traditionally based on discrete interconnected components. flip chips are delivered in tape and reel an d are fully compatible with other high volume smd components (standard plastic packages or csp/bga packages) regarding existing pick and place equipment, standard solder reflow assembly equipment and standard pcb techniques. 9 revision history table 5. document revision history date revision changes 05-aug-2013 1 first issue
AN4208 16/16 docid023948 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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